Section: New Results

Dynamic reconfiguration for HP-SoC

Context switching for volatile IP

Dynamic reconfigurations require configuration decisions from smart controllers. Such a decision implies context saving of an existing IP or switching from an IP to another (loading a new bitstream). The store/restore operations can be managed by the operating system or by using a dedicated hardware component. In this work, a new model for hardware IP context storage and management is proposed. The approach is based on a flexible hardware wrapper which can make IP reconfigurable. In fact, these wrappers contain a naming system supporting efficient runtime context switching.

A generic broadcast network for HP-SoC architecture

The hNoC model proposes a specific network on chip dedicated to the massively parallel architecture SCAC. This model is composed of huge number of complex routers, called node elements (the NEs), communicating and working in perfect synchronizations. Each NE is potentially connected to its neighbors via a regular connection. Furthermore, each NE is connected to a heterogeneous set of computing groups (clusters) allow asynchronous processing. Each group includes a combination of processors programmable, the PEs (software processing units) and specialized hardware accelerators (hardware processing units) to perform critical tasks demanding the more performance. All the system is controlled by a Network Controller Unit, the NCU. The NCU and The PEs are implemented with the Forth processor.

The aim of our works is to design a new kind of communication network model for SCAC architecture to overcome firstly the overlapping communications with computations and secondly to increase significantly the external performances in terms of throughput. The difficulty of designing hNoC is a compromise between an optimal quality of broadcasting, high bandwidth and important flexibility of use, while reducing power consumption and silicon area.

Our first contributions defined a broadcast with mask model integrated in the communication network hNoC of SCAC architecture. This model is based on subnetting the network of processing nodes which separate the control of communication and processing. Our model was implemented in synthetizable VHDL code that is simulated and targeted Xilinx Virtex6 (XC6VLX240T) board.

Distributed control for dynamic reconfiguration

The aim of our current work is to propose a distributed approach for reconfiguration control on FPGAs. The main reason for choosing a distributed control approach is that, with the ever growing complexity and size of the modern reconfigurable systems, the traditional centralized approach is no more efficient. Instead, a distributed control has many advantages in terms of performance and design efficiency. Indeed, the distributed control allows to avoid communication bottlenecks and to increase the parallelism compared to the centralized one, allowing a better performance which is a critical issue especially for high-performance applications. At the design level, the distributed control has many advantages. It allows to decrease the design complexity of the control by dividing the intelligence between the controllers, which allows a shorter design time and an easier verification. It also facilitates the reuse of the controllers instead of redesigning a centralized controller for different systems, which allows also a higher scalability in order to adapt to the growing size of the modern SoC. Our approach for reconfiguration control is an event-driven control, where events come from a variety of sources in order to ensure a high adaptivity of the reconfigurable systems. Reconfiguration can be triggered by a user input, a change in the environment condition (e.g. changes in lightening condition) or a change in performance or power consumption requirements, etc. Therefore, we propose a modular structure of each controller allowing three major tasks: monitoring, decision making and reconfiguration realization. In order to respect the global constraints of the system, the controllers communicate their decisions to each other in order to handle cooperation and conflicts. In [25] , we proposed a high-level design of our approach using Model Driven Engineering aiming to combine the advantages of the distributed control with the high-level design in order to decrease design complexity and automate code generation increasing thus design productivity.

At the physical level, the distributed control has been implemented for simple applications in order to test the different modules of the controllers (monitoring, decision making, communication between controllers). As a future work, we plan to implement the distributed control for more complex applications in order to highlight the advantages of our approach and study its limits.

Avionic test bench on heterogenous reconfigurable platform

The aim goal of this thesis is to design the next Eurocopter avionic test bench generation. For the past 20 years, Test Systems have always be considered as a must do in the avionic development cycle. In early 2008, the Eurocopter research department has undertaken a profound reflection on the vocation Pro-Active Test Systems [15] . Hitherto, the test systems were based on real time specific CPU boards that run proprietary real time operating systems and plugged with Input/Output (I/O) boards to communicate with the equipments under test. In current industrial practice, the well-spread VME CPU boards are widely used. Due to the present test system performance requirement, an increase in the computation rates is needed, but it cannot be delivered by the VME CPU boards any-more. Furthermore, this solution is considered as an expensive maintainable technology. To overcome these drawbacks, the usage of multicore hosts (PC or workstation) allows an immediate increase in the capacity of computation. An important outcome of this transition is the refusal of the obsolete CPU boards. However, this solution cannot guarantee the real-time criteria while the execution of concurrent tasks due to the lack of an appropriate Operating System (OS) environment. In addition, this solution brings new communication latencies between the CPUs and I/O boards plugged in the VME backplane. In this work, our proposal is to make profit from the new available hardware computing resource (FPGA) and to make up hybrid avionic test systems [27] . Indeed, FPGA technology could offer a higher computation rates comparing to CPUs up to 10x. It could implement heavy models in a hardware fashion with the management of the parallelism degree to answer the real-time constraints of the application. The main challenge of hybrid (CPU/FPGA) architectures concerns the programming model and the design methodology. We need to deal with the heterogeneity of both hardware and software parts in order to obtain a fast system prototyping. In current industrial practice, manual coding is still widely adopted in the development of hybrid architectures, which is clearly not suited to manage the complexity intrinsic in these systems. For designers, this approach is very tedious, error-prone and expensive. In the first part of our work we emphasized the usage of Model Driven Engineering (MDE) for heterogeneous systems in order to reduce the design complexity of CPU-FPGA architectures [72] . In ReCoSoC paper, we focused on the prototyping environment and the related development tools in order to map existing software into CPU-FPGA architectures by detecting all data dependencies and get the parallelism degree. Moreover, we presented communication solutions comparing fast links such as Ethernet and PCIe. Secondly Multi-Core optimizations in different environments such as Linux with Open Source real-time patches (Xenomai) and processor affinities capabilities. Then, we presented in [28] a new generation of adaptive and generic avionic test benches using FPGA reconfigurability capabilities. Indeed, nowadays, each Eurocopter test bench is related to a specific embedded part and a specific aircraft. Proposing such generic architecture will reduce the helicopter design cycle significantly by Testing different embedded systems at the same time.